The present invention relates to a chip design, and more particularly, to a wafer-level package having semiconductor dies supporting a flow control mechanism for implementing a high performance bus protocol on a communication bus between the semiconductor dies.
When a chip function of a target chip is achieved using a large-sized die, the fabrication of large-sized dies on a wafer will suffer from low yield and high cost. Given the same die area, the yield of one large die is lower than the yield of multiple small dies. More specifically, assuming that distribution of defects on a wafer is the same, a die yield of one large-sized die fabricated on the wafer is lower than a die yield of multiple small-sized dies which have the same area fabricated on the same wafer. However, splitting one large die into multiple smaller dies may bring some overhead. For example, a large number of signals will be introduced to achieve communications between different small-sized dies assembled in the same package. Further, a communication bus between two small-sized dies may suffer from long latency. For example, when a real-time handshaking mechanism is employed by a bus master and a bus slave, the performance of the communication bus may be degraded due to the long latency inherent to the communication bus. Thus, there is a need for an innovative bus protocol design that can achieve a high performance communication bus between multiple dies assembled in the same package.